U.S. Pat. No. 3,967,269 to Fletcher describes the general arrangement and operation of dual-flash digital-to-analog converters and discusses the various sources of errors or transfer function nonlinearities which can occur in their operation. Fletcher further discloses a digital corrective feedback circuit for detecting, in the second quantization stage, errors which occurred in the first quantization stage, and generating a digital correction signal to correct the binary output of the converter to compensate for such errors. A further analysis of such errors and methods of correcting them, using digital corrective logic, appears in W. K. Kester, "PCM Signal Codecs for Video Applications", SMPTE Journal, November, 1979, Vol. 88, pp. 770-78. In that article, Kester further describes various systems and methods of testing the performance of video A/D converters for linearity, accuracy and other performance characteristics. A. S. Muto et al., "Designing a 10 Bit, 20 Mega Sample per Second Analog to Digital Converter System", Hewlett Packard Journal, November, 1982, pp. 9-20, discloses an advanced design of a dual-flash analog-to-digital converter wherein the digital error correction is implemented by using, in the second quantizer, an extra bit which is redundant of the least significant bit from the first quantizer, and discloses an algorithm for mathematically extracting the final output code from the overlapping codes of each quantization step.
The structure and operation of the foregoing converters tends to mask internal quantization problems which arise in the operation of dual-flash analog-to-digital converters. Diagnostic information on the analog-to-digital conversion performance, such as indication of errors due to first quantizer gain or offset errors, digital to analog gain or offset errors, clock or delay timing errors, or limiter amplifier offset errors, is unavailable to aid in calibration of the converter. Aside from providing a corrected binary output signal, the aforementioned Fletcher patent only provides an instantaneous overflow-underflow signal, which is used to correct the binary output of the first parallel stage. However, monitoring this signal does not provide sufficient diagnostic information properly to calibrate the converter. In the more modern designs, disclosed in the aforementioned Kester and Muto et al. articles, even the overflow-underflow feedback signal of Fletcher is unavailable. Moreover, since these designs are conventionally executed in integrated circuits, it is impractical to probe the internal workings of the circuits to obtain the desired diagnostic information. None of the test systems and methods described by Kester meet this need.
The prior art also does not disclose any means for determining a persistent near over-range condition in the first quantizer. Finally, none of the aforementioned converter designs provide for clipping, digitally or otherwise, to deliberately introduce nonlinearities into the transfer functions of the converters. This capability would be particularly useful for digitizing video signals.